Alex Bashara

Multicore Interfence Analysis

This project was my senior desgin project that was overseen by Boeing. The goal of this project was to identify architectural interfence channels, bound the worst case execution time, and show how effective different interference mitigation techniques are in a Xen hypervisor. We used a multicore ARM processor and ran multiple tasks on it to see how they would interfere with each other. We used a combination of open source tools as well as some self written programs to stress the system and monitor the performance. For this project, I was the Embedded Systems Engineer and helped with the hardware bringup as well as worked on the cache interfence channel by writing interference generators and studying ARM architectures. I learned a lot about shared resouces and how they can interfere with each other as well as ARM architectures. This project allows for Boeing to validate multicore systems and understand how they can be used in safety critical systems.

Multicore Operational Analysis Tooling

Real-Time Telemetry System

When I joined the Cyclone Racing Formula SAE Team in 2021, the team had never had a wireless telemetry system. Another engineer and I set out to build one. In the first year, we managed to create a basic AVR based system that was able to collect data from the ECU, send it wirelessly in real time, and display it on a computer. In the second year, we improved the system by creating a custom PCB as well as adding a dash display for the driver and a new sensors such as brake temp and accelerometers. In the third year, we moved the system to an ARM based platform, creating custom microcontroller PCBs. This allowed us much more control over the funcionality of the system as well as allowed us implement a RTOS to help manage our Real-Time requirements.

Link to Cyclone Racing's GitHub

Simulated MIPS VHDL Processor

For this project, my group and I were tasked with creating three different architectures for a MIPS Processor: a single cycle structure, a software pipeline, and a hardware pipeline. We started with the single cycle architecture by creating a VHDL file for each component of the processor. We then moved on to the software pipeline, which was a bit more challenging. We had to create a control unit that would be able to handle the different stages of the pipeline. Finally, we moved on to the hardware pipeline. This was the most challenging part of the project. We had to create a control unit that would be able to handle the different stages of the pipeline. We also had to create a forwarding unit to handle data hazards.

Vivado Projects

One of the classes that I choose to take was Embedded Systems Design. In this class, other engineers and I were tasked with creating multiple FPGA based projects including an NES Emulator, Drone Controller, Camera System, and an Embedded Linux Driver. For these projects we used a Zynq 7000 SoC and Vivado to create the projects. We also used the Xilinx Vitis SDK to write the embedded software. This class was a great learning experience and I was able to learn a lot about embedded systems and FPGA design.